IBM Research has unveiled NanoStack, a sequential stacking CMOS transistor architecture that essentially builds chips upward like skyscrapers rather than sprawling them outward like suburbs. The design targets what the company calls the CMOS 7A node and beyond, promising roughly 50% area scaling compared to IBM’s existing 2 nm technology.

What NanoStack actually does

The architecture introduces several innovations that distinguish it from prior approaches to vertical chip integration. NanoStack allows flexible positioning of top and bottom nanosheet channels, meaning engineers can optimize where transistors sit within the stack based on performance requirements rather than being locked into rigid configurations.

It also features a thermally stable bottom FET gate stack. This has historically been one of the hardest problems in stacking transistors vertically, because building new layers on top of existing ones subjects everything below to additional thermal stress.

Thin dielectric bonding ties the layers together, creating what IBM describes as a manufacturable sequential multi-channel approach.

The projected performance numbers are striking. For 4-track base cells, IBM estimates approximately 50% area reduction and a comparable performance uplift at iso-power compared to the current 2 nm node. Perhaps more impressive: nearly 70% power reduction at iso-performance.

The Lam Research partnership and Albany NanoTech

On March 10, 2026, IBM announced a partnership with Lam Research focused on advancing the process development necessary for both nanosheet and nanostack devices. The work is happening at IBM’s Albany NanoTech Complex. The partnership with Lam specifically targets validation of full process flows using advanced manufacturing platforms.

IBM has credibility here. The company unveiled the first 2 nm chip back in 2021, establishing itself as a leader in pushing the boundaries of transistor density. NanoStack represents the next logical step beyond previous CFET-style implementations, which stacked complementary transistors but with more constraints on channel placement and thermal management.

What this means for investors

The NanoStack paper was first presented at the 2025 VLSI Technology and Circuits Symposium, and the technology targets nodes that are still years away from volume production.

A 50% area reduction means more compute per chip. A 70% power reduction at iso-performance means data centers can either run the same workloads for less money or run significantly more demanding workloads within existing power envelopes.