The semiconductor arms race just got a new battleground. Intel is developing a dual-sided power delivery architecture for its 14A2 process node, a design shift driven by the physics of cramming interconnects down to 21nm spacing. The move positions Intel directly against TSMC’s A14 and Samsung’s SF1.4 and SF2Z programs in what is shaping up to be the most consequential chipmaking competition in years.

Here’s the thing: when you shrink interconnect pitch to 21nm, the old way of routing power through the front side of a chip starts working against you. The wires that carry power compete for space with the wires that carry signals, and at 21nm, that tradeoff becomes untenable. Intel’s answer is to split the job across both sides of the chip.

What dual-sided power delivery actually means

Intel’s implementation will pair its PowerDirect BSPDN technology with front-side metal layers that handle signal and clock delivery. Power comes up from the bottom, data moves across the top, and the two systems stop tripping over each other.

Intel has already been developing BSPDN capability through its PowerVia technology on existing process nodes. The 14A2 program represents the first time that work gets integrated into a leading-edge production node at volume scale.

The broader industry has arrived at the same conclusion independently. TSMC introduced its Super PowerRail architecture for the A16 node. Samsung is incorporating BSPDN into its SF2 and SF2Z programs.

Timeline: who gets there first

Samsung currently holds the earliest timestamp in this race. The Korean chipmaker is targeting risk production of its SF2Z backside-power node as early as 2027, with full mass production planned for 2029.

TSMC’s A14 node is targeting high-volume manufacturing in 2028.

Intel’s 14A2 risk production is projected to begin in 2028, with high-volume manufacturing following in 2029. Risk production is the semiconductor industry’s term for early manufacturing runs used to validate yields before committing to full-scale output.

Intel’s 14A node, the predecessor, is designed to deliver roughly 1.3 times higher chip density compared to the 18A node. The 14A2 variant tightens interconnect pitch further to 21nm, which is where the power delivery redesign becomes necessary.

Why semiconductor investors should be paying attention

For Intel, the 14A2 program is as much about rebuilding foundry credibility as it is about process leadership. A 2028 risk production target, if achieved, would be a signal that Intel’s turnaround narrative has tangible technical substance behind it.

Samsung’s SF2Z timeline, if the 2027 risk production target holds, would give Samsung a brief first-mover window at the 1.4nm class.

Dual-sided power delivery directly improves performance-per-watt by reducing resistance in power delivery paths and reclaiming front-side routing resources for logic.

Investors watching semiconductor sector valuations will want to track two leading indicators as 2027 approaches. First, customer tape-out announcements: when a major fabless company commits a design to a specific foundry node, it is a hard signal about which manufacturer they believe will deliver. Second, yield data from risk production runs, which companies occasionally disclose indirectly through commentary on manufacturing margins.