IonQ runs first real-time quantum error correction decoder on a single commodity CPU

Quantum error correction has long been the unglamorous but utterly essential plumbing of any future fault-tolerant quantum computer. IonQ just demonstrated something that could make that plumbing a lot cheaper to install.

Researchers Min Ye, Andrii Maksymov, and Nicolas Delfosse at IonQ have built what they describe as the first real-time quantum error correction (QEC) decoding pipeline that runs entirely on general-purpose hardware: specifically, a single 2024 Apple M4 Max CPU. Their work, detailed in an arXiv paper (arXiv:2608.25027) published on August 25, 2026, showed the system handling simulated workloads scaling up to 408 logical qubits while executing over 1 million T gates and 1.3 million logical measurements.

Why a commodity CPU matters

To understand why this is a big deal, consider the traditional assumption in quantum computing circles. As quantum systems grow, the classical computers responsible for decoding error syndromes in real time would need to keep pace. The fear was that this classical overhead would become a bottleneck, requiring expensive, purpose-built hardware like FPGAs (field-programmable gate arrays) or ASICs (application-specific integrated circuits) to keep up with the quantum processor’s output.

The team used 12 out of 16 cores on the Apple M4 Max for their processing workloads. At realistic physical error rates (p_CNOT = 10^{-4}), the real-time decoding pipeline introduced a computational stretch of less than 0.3%. Even at a higher error rate of p_CNOT = 5×10^{-4}, the stretch stayed below 12%.

This is the first time anyone has demonstrated a full-scale real-time decoder for large fault-tolerant workloads running on off-the-shelf hardware. Every previous attempt at real-time decoding at meaningful scale required specialized accelerators.

The dual-decoder architecture

The secret sauce is a dual-decoder architecture that splits the error correction work into two parallel streams: continuous error correction and low-latency outcome decoding. The continuous correction layer handles the ongoing stream of syndrome data, the noisy diagnostic signals that tell the system where errors might be lurking. The outcome decoder jumps in when logical measurements need to be resolved quickly, keeping the system responsive without creating a pileup.

IonQ’s approach leans into a natural advantage of trapped-ion quantum computing. Syndrome extraction cycle times in trapped-ion systems range from 1 to 5 milliseconds, which is orders of magnitude slower than superconducting qubit architectures. That gives the classical decoder more breathing room to process each round of syndrome data.

From simulation to roadmap

An important caveat: no physical quantum computer running at this scale was involved. The results came from simulated workloads designed to match IonQ’s proposed architecture. The paper is a proof of concept for the classical side of the equation, not a claim about quantum hardware readiness.

That said, the work aligns directly with IonQ’s Walking Cat fault-tolerant architecture, which the company published in April 2026. Walking Cat lays out a blueprint for scaling to over 10,000 physical qubits. Demonstrating that the classical decoding layer can handle workloads of this magnitude on a consumer-grade chip validates a critical piece of that blueprint.

What this means for the quantum computing landscape

The broader implication is economic as much as technical. If large-scale quantum error correction can run on hardware you’d find in a high-end laptop, the cost structure for building fault-tolerant quantum systems shifts meaningfully. Custom FPGA or ASIC development is expensive, time-consuming, and creates additional supply chain dependencies.

Competitors working with superconducting qubits, where syndrome extraction cycles are measured in microseconds rather than milliseconds, face a much harder version of this same classical decoding challenge.

The transition from simulated workloads to real hardware execution remains the next critical test. If IonQ can replicate these decoding results alongside an actual trapped-ion processor operating at the target error rates, it would represent one of the most significant de-risking events in the fault-tolerant quantum computing timeline to date.