Credo Technology achieves PCI-SIG 6.x compliance for Toucan retimer, eyeing AI infrastructure boom
The semiconductor firm's latest PCIe retimer hit 64.0 GT/s compliance, a key milestone for next-generation AI accelerator platforms and high-performance computing.
Credo Technology Group (NASDAQ: CRDO) announced that its Toucan Gen6x16 PCIe retimer has passed PCI-SIG 6.x compliance testing at 64.0 GT/s. The certification, formalized on August 31, 2026, followed testing that wrapped up at a PCI-SIG Compliance Workshop on July 31, 2026.
The device now qualifies for the PCI-SIG Integrators List, which tells hyperscalers and system builders the hardware meets strict standards for electrical and protocol requirements.
What the Toucan retimer actually does
A retimer sits between two endpoints on a PCIe bus and cleans up the electrical signal as it travels across a circuit board or cable, restoring it before errors pile up.
Credo’s Toucan handles 16 lanes running at up to 64.0 GT/s using PAM4 signaling. That throughput matters in environments where insertion loss exceeds 36 to 40 dB. Dense GPU clusters and AI accelerator platforms are exactly those environments.
The device is built on a 7 nm process node, draws a typical 11 W for x16 operations, and clocks in at under 7 ns of latency.
Beyond PCIe 6.x, the Toucan also supports CXL 3.x, and is backward-compatible with earlier PCIe generations while aligning with the future PCIe 7.0 roadmap.
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Building on earlier milestones
This isn’t Credo’s first compliance win with the Toucan platform. Back in February 2026, the same device passed PCI-SIG compliance at 32.0 GT/s, corresponding to the PCIe 5.0 standard.
Vishal Shah, Credo’s VP of Product, framed the 64.0 GT/s milestone as validation of signal integrity and interoperability for next-generation AI infrastructure.
Credo Technology specializes in high-speed SerDes (serializer/deserializer) and connectivity solutions.
Why AI infrastructure needs better retimers
PCIe 6.x doubles the bandwidth of PCIe 5.0, jumping from 32.0 GT/s to 64.0 GT/s per lane. For a x16 link, that translates to roughly 128 GB/s of raw bidirectional bandwidth.
The CXL 3.x support allows multiple processors to access a shared pool of memory, reducing waste and improving utilization across AI workloads that push memory requirements beyond what individual servers can economically provide.
Competitors including Astera Labs and Microchip Technology are pursuing similar PCIe 6.x and CXL solutions. Credo’s compliance at 64.0 GT/s while keeping power at 11 W and latency below 7 ns gives it specific, measurable differentiators to bring to competitive evaluations.