Nvidia considers reducing memory in next-gen Rubin Ultra GPU

Nvidia is weighing a significant spec change to its upcoming Rubin Ultra GPU, potentially shipping the chip with far less high-bandwidth memory than the company originally targeted. The adjustment, reported by TrendForce in early August 2026, is a direct response to tightening supply of HBM from the three major producers: SK Hynix, Samsung, and Micron.

The original vision for Rubin Ultra was ambitious. When Nvidia first unveiled the chip at its GTC developer conference in 2025, configurations on the table included up to 1 TB of HBM4E memory. The current Vera Rubin GPU, already in mass production, ships with up to 288 GB of HBM4 in 12-Hi stacks, delivering roughly 22 TB/s of memory bandwidth. Rubin Ultra was supposed to push well past that.

Now, Nvidia is testing at least three variants with meaningfully reduced memory. One configuration under review uses 8-Hi HBM4 stacks carrying approximately 192 GB of memory. Compared to the 288 GB on the current Vera Rubin, that is a 33% reduction in on-chip memory for a chip that was supposed to represent a generational leap forward.

Why memory is everything for AI workloads

High-bandwidth memory is not just about capacity. The “bandwidth” part refers to how fast data moves between the memory and the chip’s processing cores. At 22 TB/s, the current Vera Rubin already operates at speeds that dwarf conventional server memory by orders of magnitude.

A shift to 8-Hi stacks from 12-Hi stacks reduces both capacity and, potentially, bandwidth. Nvidia is reportedly testing variants to ensure peak performance is preserved despite the memory reduction, but the physics of fewer memory stacks impose real limits on what engineering optimizations can recover.

TrendForce’s August 4 report noted that Nvidia is evaluating four distinct HBM configurations for Rubin Ultra, with the pivot away from 12-Hi HBM4E driven by anticipated DRAM and HBM shortages expected to deepen into 2027. Yield and production challenges at all three major HBM suppliers have created a wafer allocation bottleneck that Nvidia cannot resolve unilaterally.

The hidden cost of doing more with less

If Rubin Ultra ships with less memory per GPU, enterprises running very large AI models will likely need more GPUs to handle the same workloads. A model that fits on four high-memory GPUs might require six or eight lower-memory ones, with the additional hardware bringing its own costs: more power consumption, more rack space, more interconnect infrastructure, and more licensing overhead.

There is a nuance for Nvidia’s revenue picture as well. HBM4E, the higher-spec memory originally planned for Rubin Ultra, commands higher margins throughout the supply chain. A shift toward lower-tier HBM configurations affects demand for the most profitable memory products, which in turn affects how SK Hynix, Samsung, and Micron prioritize their production roadmaps.

HBM supply is already tight enough that allocation decisions by memory manufacturers carry real geopolitical and competitive weight. Nvidia is the dominant buyer, but it competes for wafer capacity against AMD, Google, and a growing roster of custom AI chip programs from hyperscalers like Amazon, Microsoft, and Meta.

What this means for the AI chip market

Leading-edge HBM requires extremely precise stacking of DRAM dies, and yield rates for 12-Hi configurations are lower than for the simpler 8-Hi stacks, creating production bottlenecks that cannot be solved quickly.

The memory suppliers, meanwhile, face their own strategic calculations. Tight HBM supply into 2027 keeps pricing elevated and demand strong, but customers being forced to buy more GPUs to compensate for memory reductions creates pressure to eventually close the supply gap. The company that figures out higher-yield 12-Hi or 16-Hi stacking first will have significant leverage in the next round of GPU design negotiations.