Google splits its eighth-generation TPU into two chips for training and inference
Google / Wikimedia Commons (Public domain)
The TPU 8t targets massive pre-training runs while the TPU 8i is built for memory-hungry inference and reasoning workloads
Google has stopped trying to build one AI chip that does everything. At Google Cloud Next on April 22, 2026, the company unveiled its eighth-generation Tensor Processing Units as two separate designs: the TPU 8t for large-scale pre-training and the TPU 8i for inference and high-concurrency reasoning.
It marks the first time Google has split a TPU generation into distinct designs.
The timing reflects where AI is heading. Google framed the launch around the so-called “agentic era,” where AI systems no longer just answer one prompt. They juggle many tasks at once, and that puts very different demands on hardware than training a model does.
Two chips, two jobs
Some quick vocabulary helps here. Training is when a model learns from enormous datasets, a process that rewards raw computing muscle at huge scale. Inference is when the finished model actually answers questions, which rewards memory, speed and cost efficiency because it happens constantly.
The TPU 8t is the heavyweight. Google says it can scale to superpods of up to 9,600 chips, delivering 121 ExaFlops using FP4.
Per chip, the TPU 8t delivers 12.6 FP4 PFLOPs. It pairs 216 GB of High Bandwidth Memory (HBM) with 128 MB of Static Random-Access Memory (SRAM).
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The TPU 8i carries 288 GB of HBM and 384 MB of SRAM, which Google says is three times the SRAM of the previous generation. Its compute comes in at 10.1 FP4 PFLOPs per chip.
Google’s headline efficiency claim for the TPU 8i is up to 80% better performance-per-dollar than the Ironwood generation.
What’s under the hood
Both chips are manufactured on TSMC’s N3 process technology. Both also integrate Google’s own Arm-based Axion CPUs, and they slot into the company’s broader AI Hypercomputer architecture.
The TPU 8i adds a couple of design specifics of its own. It uses a new Boardfly topology, which governs how chips are wired to talk to one another, along with a CAE engine that Google says boosts performance.
On the software side, Google is emphasizing tighter coordination between hardware and tooling through frameworks like JAX and Pathways.
The eighth generation follows Ironwood, the seventh-generation TPU that launched in 2025. Google expects general availability of the new chips later in 2026, and the company plans to share more technical details at Hot Chips 2026 in August.
Disclosure: This article was edited by Diego Almada Lopez. For more information on how we create and review content, see our Editorial Policy.

