Microchip and Micron unveil PCIe Gen 6 storage built for the AI era

Via amazon.com

Microchip and Micron unveil PCIe Gen 6 storage built for the AI era

The two chipmakers demonstrated an end-to-end Gen 6 storage architecture at FMS 2026, pairing the industry's first mass-production PCIe Gen 6 data center SSD with next-generation switching silicon.

At the Future of Memory and Storage Conference on August 4, 2026, Microchip Technology and Micron Technology jointly demonstrated a full end-to-end PCIe Gen 6 storage architecture, combining Micron’s 9650 NVMe SSDs with Microchip’s Switchtec Gen 6 PCIe fanout switches. The result is a system where multiple SSDs can all run simultaneously at full Gen 6 speeds, rather than sharing a constrained bus.

What Gen 6 actually means in practice

PCIe Gen 6 doubles the transfer rate of its predecessor to 64 gigatransfers per second per lane.

Micron’s 9650 SSD is the first PCIe Gen 6 data center SSD to reach mass production, and it demonstrates sequential read speeds of up to roughly 28 GB/s.

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The Microchip Switchtec Gen 6 switches support up to 160 lanes. They are built on a 3 nm process. The switches also include hardware root of trust, advanced error containment, multicast support, and CNSA 2.0 post-quantum-safe cryptography.

Why the AI and cloud markets care

Brian McCarson from Microchip framed the announcement around ecosystem cohesion, arguing that storage and switching solutions need to be designed together rather than bolted together after the fact. Larry Hart from Micron linked the announcement directly to AI infrastructure, noting that storage performance needs to keep pace with what increasingly complex AI models actually demand at the hardware level.

A PCIe Gen 6 SSD plugged into a Gen 5 switch is leaving performance on the table. A Gen 6 switch with Gen 5 drives is similarly neutered. The value here is in the end-to-end validation, where Microchip and Micron have jointly confirmed that their respective hardware operates at full throughput together, reducing the integration risk for data center operators who would otherwise have to figure that out themselves.

What this means for investors watching MCHP and MU

Microchip Technology trades on Nasdaq under the ticker MCHP, and Micron trades as MU.

Micron’s 9650 being the first Gen 6 data center SSD in mass production is a meaningful moat, at least temporarily. Being first to mass production in a new interface generation gives a vendor the opportunity to lock in design wins with major cloud customers before competitors arrive.

The post-quantum cryptography inclusion in the Switchtec switches is worth flagging for investors with a longer time horizon. Governments and regulated industries are beginning to require quantum-resistant security in infrastructure hardware, and having CNSA 2.0 compliance built into a shipping product is a potential differentiator as those procurement requirements become more common.

Disclosure: This article was edited by Editorial Team. For more information on how we create and review content, see our Editorial Policy.

Microchip and Micron unveil PCIe Gen 6 storage built for the AI era

Microchip and Micron unveil PCIe Gen 6 storage built for the AI era

The two chipmakers demonstrated an end-to-end Gen 6 storage architecture at FMS 2026, pairing the industry's first mass-production PCIe Gen 6 data center SSD with next-generation switching silicon.

Via amazon.com

At the Future of Memory and Storage Conference on August 4, 2026, Microchip Technology and Micron Technology jointly demonstrated a full end-to-end PCIe Gen 6 storage architecture, combining Micron’s 9650 NVMe SSDs with Microchip’s Switchtec Gen 6 PCIe fanout switches. The result is a system where multiple SSDs can all run simultaneously at full Gen 6 speeds, rather than sharing a constrained bus.

What Gen 6 actually means in practice

PCIe Gen 6 doubles the transfer rate of its predecessor to 64 gigatransfers per second per lane.

Micron’s 9650 SSD is the first PCIe Gen 6 data center SSD to reach mass production, and it demonstrates sequential read speeds of up to roughly 28 GB/s.

Advertisement

The Microchip Switchtec Gen 6 switches support up to 160 lanes. They are built on a 3 nm process. The switches also include hardware root of trust, advanced error containment, multicast support, and CNSA 2.0 post-quantum-safe cryptography.

Why the AI and cloud markets care

Brian McCarson from Microchip framed the announcement around ecosystem cohesion, arguing that storage and switching solutions need to be designed together rather than bolted together after the fact. Larry Hart from Micron linked the announcement directly to AI infrastructure, noting that storage performance needs to keep pace with what increasingly complex AI models actually demand at the hardware level.

A PCIe Gen 6 SSD plugged into a Gen 5 switch is leaving performance on the table. A Gen 6 switch with Gen 5 drives is similarly neutered. The value here is in the end-to-end validation, where Microchip and Micron have jointly confirmed that their respective hardware operates at full throughput together, reducing the integration risk for data center operators who would otherwise have to figure that out themselves.

What this means for investors watching MCHP and MU

Microchip Technology trades on Nasdaq under the ticker MCHP, and Micron trades as MU.

Micron’s 9650 being the first Gen 6 data center SSD in mass production is a meaningful moat, at least temporarily. Being first to mass production in a new interface generation gives a vendor the opportunity to lock in design wins with major cloud customers before competitors arrive.

The post-quantum cryptography inclusion in the Switchtec switches is worth flagging for investors with a longer time horizon. Governments and regulated industries are beginning to require quantum-resistant security in infrastructure hardware, and having CNSA 2.0 compliance built into a shipping product is a potential differentiator as those procurement requirements become more common.

Disclosure: This article was edited by Editorial Team. For more information on how we create and review content, see our Editorial Policy.