SK hynix, Solidigm and others pitch AI memory beyond HBM at OCP Global Summit

AI models have a memory problem. At the 2026 Open Compute Project Global Summit, four hardware companies showed up with different answers to it.

SK hynix, Metrum AI, Solidigm and Nallasway each presented systems that push AI memory past a single tier of high-bandwidth memory, or HBM. The shared message was simple: the fast memory sitting on the processor package is no longer enough for where AI workloads are going.

The summit ran from October 12 to 15 in San Jose and drew a record crowd of around 15,000 attendees.

What each company brought to San Jose

The pressure comes from agentic AI. These are systems that take on multi-step tasks and hold long, multi-turn conversations with users or other software.

Every turn adds to what engineers call the key-value cache, or KV cache. Those notes grow large, and they have to live somewhere fast.

SK hynix introduced its Memory-centric AI Rack System, which it calls MARS. Alongside it, the company showed CXL 3.2-based 256 GB CMM-DDR5 modules.

CXL, short for Compute Express Link, is a standard that lets processors reach memory sitting outside their own package.

SK hynix says the new modules deliver 80 GB/s of bandwidth. The company also claims roughly 30% better energy efficiency compared to previous generations.

Metrum AI and Solidigm took a different route. Their joint demo used a shared SSD pool to hold the KV cache, offloading it from more expensive memory onto solid-state storage.

The reported results were eye-catching. The setup achieved up to 64.8 times faster time-to-first-token, which measures how long a model takes to start producing its answer.

The pair also reported 40.7 times higher throughput. Energy use per GPU request fell by 26.5 times compared to traditional methods.

Nallasway proposed connecting external DRAM modules directly to XPUs, a catch-all term for AI processors of various types. Its proposed XPU module enables a 3.2 TB memory expansion using LPDDR5X DRAM.

Why HBM alone is running out of road

That design is fast. It is also finite. You can only fit so much memory onto a package, and agentic workloads keep asking for more.

The OCP presentations point to two techniques emerging as answers. The first is CXL pooling, where multiple processors share a larger reserve of memory. The second is SSD offloading, where less urgent data moves down to storage.

Both lead to the same destination: disaggregated, tiered memory. Instead of each processor owning a fixed slice, memory becomes a shared resource arranged in layers, from fastest and priciest to slower and cheaper.

What this means for the AI hardware stack

SK hynix is already deep in the HBM business, and MARS shows it planning for a world where HBM is one tier among several.

The energy numbers may end up mattering more than the speed figures. SK hynix’s claimed 30% efficiency gain and Metrum AI and Solidigm’s reported 26.5 times reduction in energy per GPU request both speak to the cost of running AI at scale.

These are proposals and demonstrations, not confirmed deployments. Software also has to keep up. Spreading memory across CXL pools, DRAM modules and SSDs only pays off if the stack knows what data belongs where, and when to move it.